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19-1259; Rev 0; 7/97
SPI/Microwire-Compatible UART in QSOP-16
_______________General Description
The MAX3100 universal asynchronous receiver transmitter (UART) is the first UART specifically optimized for small microcontroller-based systems. Using an SPITM/MicrowireTM interface for communication with the host microcontroller (C), the MAX3100 comes in a compact 16-pin QSOP. The asynchronous I/O is suitable for use in RS-232, RS-485, IR, and opto-isolated data links. IR-link communication is easy with the MAX3100's infrared data association (IrDA) timing mode. The MAX3100 includes a crystal oscillator and a baudrate generator with software-programmable divider ratios for all common baud rates from 300 baud to 230k baud. A software- or hardware-invoked shutdown lowers quiescent current to 10A, while allowing the MAX3100 to detect receiver activity. An 8-word-deep first-in/first-out (FIFO) buffer minimizes processor overhead. This device also includes a flexible interrupt with four maskable sources, including address recognition on 9-bit networks. Two hardware-handshaking control lines are included (one input and one output). The MAX3100 is available in 14-pin plastic DIP and small, 16-pin QSOP packages in the commercial and extended temperature ranges.
____________________________Features
o 16-Pin QSOP Package (8-pin SO footprint): Smallest UART Available o Full-Featured UART: --IrDA SIR Timing Compatible --8-Word FIFO Minimizes Processor Overhead at High Data Rates --Up to 230k Baud with a 3.6864MHz Crystal --9-Bit Address-Recognition Interrupt --Receive Activity Interrupt in Shutdown o SPI/Microwire-Compatible C Interface o Lowest Power: --150A Operating Current at 3.3V --10A in Shutdown with Receive Interrupt o +2.7V to +5.5V Supply Voltage in Operating Mode o Schmitt-Trigger Inputs for Opto-Couplers o TX and RTS Outputs Sink 25mA for Opto-Couplers
MAX3100
______________Ordering Information
PART MAX3100CPD MAX3100CEE MAX3100EPD MAX3100EEE TEMP. RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C PIN-PACKAGE 14 Plastic DIP 16 QSOP 14 Plastic DIP 16 QSOP
________________________Applications
Hand-Held Instruments Intelligent Instrumentation UART in SPI Systems Small Networks in HVAC or Building Control Isolated RS-232/RS-485: Directly Drives Opto-Couplers Low-Cost IR Data Links for Computers/Peripherals
Typical Operating Circuit appears at end of data sheet.
__________________________________________________________Pin Configurations
TOP VIEW
DIN 1 DOUT 2 SCLK 3 CS 4 IRQ 5 SHDN 6 GND 7 14 VCC 13 TX 12 RX DIN 1 DOUT 2 SCLK 3 CS 4 N.C. 5 IRQ 6 SHDN 7 GND 8 16 VCC 15 TX 14 RX
MAX3100
11 RTS 10 CTS 9 8 X1 X2
MAX3100
13 RTS 12 N.C. 11 CTS 10 X1 9 X2
DIP QSOP
SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
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SPI/Microwire-Compatible UART in QSOP-16 MAX3100
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................................+6V Input Voltage to GND (CS, SHDN, X1, CTS, RX, DIN, SCLK) ....-0.3V to (VCC + 0.3V) Output Voltage to GND (DOUT, RTS, TX, X2) ..............................-0.3V to (VCC + 0.3V) IRQ...........................................................................-0.3V to 6V TX, RTS Output Current ....................................................100mA X2, DOUT, IRQ Short-Circuit Duration (to VCC or GND) .........................................................Indefinite Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.00mW/C above +70C) .......... 800mW QSOP (derate 8.30mW/C above +70C) .....................667mW Operating Temperature Ranges MAX3100C_ _ ......................................................0C to +70C MAX3100E_ _ ...................................................-40C to +85C Storage Temperature Range ............................ -65C to +160C Lead Temperature (soldering, 10sec) ............................ +300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured at 9600 baud at TA = +25C.) PARAMETER Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Input Capacitance OSCILLATOR INPUT (X1) Input High Voltage Input Low Voltage Input Current Input Capacitance OUTPUTS (DOUT, TX, RTS) Output High Voltage Output Low Voltage Output Leakage Output Capacitance IRQ OUTPUT (Open Drain) Output Low Voltage Output Leakage Output Capacitance POWER REQUIREMENTS VCC Supply Current in Normal Mode VCC Supply Current in Shutdown Supply Voltage 2 ICC With 1.8432MHz crystal; all other logic inputs are at 0V or VCC SHDN bit = 1 or SHDN = 0, logic inputs are at 0V or VCC 2.7 VCC = 5V VCC = 3.3V 0.27 0.15 1 mA 0.4 10 5.5 A V VOL ILK COUT ISINK = 4mA V IRQ = 5.5V 5 0.4 1 V A pF VOH VOL ILK COUT ISOURCE = 5mA ISOURCE = 25A, TX only TX, RTS: ISINK = 25mA DOUT, TX, RTS: ISINK = 4mA DOUT only, CS = VCC 5 VCC - 0.5 VCC - 0.5 0.9 0.4 1 V V A pF VIH VIL IIN CIN VX1 = 0V and 5.5V VX1 = 0V and 5.5V Active mode Shutdown mode 5 0.7 x VCC VCC / 2 VCC / 2 0.2 x VCC 25 2 V V A pF SYMBOL VIH VIL VHYST IIL CIN 5 VCC = 3.3V 0.05 x VCC 1 CONDITIONS MIN 0.7 x VCC 0.3 x VCC TYP MAX UNITS V V V A pF LOGIC INPUTS (DIN, SCLK, CS, SHDN, CTS, RX)
ICC VCC
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SPI/Microwire-Compatible UART in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER AC TIMING (Figure 1) CS Low to DOUT Valid CS High to DOUT Tri-State CS to SCLK Setup Time CS to SCLK Hold Time SCLK Fall to DOUT Valid DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Period SCLK High Time SCLK Low Time SCLK Rising Edge to CS Falling CS Rising Edge to SCLK Rising CS High Pulse Width Output Rise Time Output Fall Time tDV tTR tCSS tCSH tDO tDS tDH tCP tCH tCL tCS0 tCS1 tCSW tr tf TX, RTS, DOUT: CLOAD = 100pF TX, RTS, DOUT, IRQ: CLOAD = 100pF (Note 1) (Note 1) CLOAD = 100pF 100 0 238 100 100 100 200 200 10 10 CLOAD = 100pF CLOAD = 100pF, R CS = 10k 100 0 100 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3100
Note 1: tCS0 and tCS1 specify the minimum separation between SCLK rising edges used to write to other devices on the SPI bus and the CS used to select the MAX3100. A separation greater than tCS0 and tCS1 ensures that the SCLK edge is ignored.
CS tCSS tCH
*** tCSH *** tDS tDH
tCSH SCLK
tCL
DIN tDV DOUT
*** tDO *** tTR
Figure 1. Detailed Serial-Interface Timing
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SPI/Microwire-Compatible UART in QSOP-16 MAX3100
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3100-01
SHUTDOWN CURRENT vs. TEMPERATURE
MAX3100-02
SUPPLY CURRENT vs. EXTERNAL CLOCK FREQUENCY
600 SUPPLY CURRENT (A) 500 400 300 200 100 0 VCC = 5V VCC = 3.3V
MAX3100-03
1000 900 800 SUPPLY CURRENT (A) 700 600 500 400 300 200 100 0 -40 -20 0 20 40 60 80 VCC = 3.3V VCC = 5V 1.8432MHz CRYSTAL TRANSMITTING AT 115.2 kbps
10 9 SHUTDOWN CURRENT (A) 8 7 6 5 4 3 2 1 0 VCC = 3.3V -40 -20 0 20
1.8432MHz CRYSTAL
700
VCC = 5V
100
40
60
80
100
0
1
2
3
4
5
TEMPERATURE (C)
TEMPERATURE (C)
EXTERNAL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT vs. BAUD RATE
1.8432 MHz CRYSTAL 5V TRANSMITTING 5V STANDBY
MAX3100-03a
TX, RTS, DOUT OUTPUT CURRENT vs. OUTPUT LOW VOLTAGE (VCC = 3.3V)
MAX3100-04
TX, RTS, DOUT OUTPUT CURRENT vs. OUTPUT LOW VOLTAGE (VCC = 5V)
80 OUTPUT SINK CURRENT (mA) 70 60 50 40 30 20 10 0 DOUT RTS TX
MAX3100-05
400 350 SUPPLY CURRENT (A) 300 250 200 150 100 50 100 1000 10k BAUD RATE (bps) 100k 3V TRANSMITTING 3V STANDBY
70 60 OUTPUT SINK CURRENT (mA) 50 40 30 20 10 0 DOUT RTS TX
90
1M
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VOLTAGE (V)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VOLTAGE (V)
4
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SPI/Microwire-Compatible UART in QSOP-16
______________________________________________________________Pin Description
PIN QSOP 1 2 3 4 6 7 8 9 10 11 13 14 15 16 5, 12 DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- NAME DIN DOUT SCLK CS IRQ SHDN GND X2 X1 CTS RTS RX TX VCC N.C. FUNCTION SPI/Microwire Serial-Data Input. Schmitt-trigger input. SPI/Microwire Serial-Data Output. High impedance when CS is high. SPI/Microwire Serial-Clock Input. Schmitt-trigger input. Active-Low Chip-Select Input. DOUT goes high impedance when CS is high. IRQ, TX, and RTS are always active. Schmitt-trigger input. Active-Low Interrupt Output. Open-drain interrupt output to microprocessor. Hardware-Shutdown Input. When shut down (SHDN = 0), the oscillator turns off immediately without waiting for the current transmission to end, reducing supply current to just leakage currents. Ground Crystal Connection. Leave X2 unconnected for external clock. See Crystal-Oscillator Operation--X1, X2 Connection section. Crystal Connection. X1 also serves as an external clock input. See Crystal-Oscillator Operation--X1, X2 Connection section. General-Purpose Active-Low Input. Read via the CTS register bit; often used for RS-232 clearto-send input (Table 1). General-Purpose Active-Low Output. Controlled by the RTS register bit. Often used for RS-232 request-to-send output or RS-485 driver enable. Asynchronous Serial-Data (receiver) Input. The serial information received from the modem or RS-232/RS-485 receiver. A transition on RX while in shutdown generates an interrupt (Table 5). Asynchronous Serial-Data (transmitter) Output Positive Supply Pin (2.7V to 5.5V) No Connection. Not internally connected.
MAX3100
_______________Detailed Description
The MAX3100 universal asynchronous receiver transmitter (UART) interfaces the SPI/Microwire-compatible, synchronous serial data from a microprocessor (P) to asynchronous, serial-data communication ports (RS232, RS-485, IrDA). Figure 2 shows the MAX3100 functional diagram. The MAX3100 combines a simple UART and a baud-rate generator with an SPI interface and an interrupt generator. Configure the UART by writing a 16-bit word to a write-configuration register, which contains the baud rate, data-word length, parity enable, and enable of the 8-word receive first-in/first-out (FIFO). The write configuration selects between normal UART timing and IrDA timing, controls shutdown, and contains 4 interrupt mask bits. Transmit data by writing a 16-bit word to a write-data register, where the last 7 or 8 bits are actual data to be transmitted. Also included is the state of the transmitted parity bit (if enabled). This register controls the state of
the RTS output pin. Received words generate an interrupt if the receive-bit interrupt is enabled. Read data from a 16-bit register that holds the oldest data from the receive FIFO, the received parity data, and the logic level at the CTS input pin. This register also contains a bit that is the framing error in normal operation and a receive-activity indicator in shutdown. The baud-rate generator determines the rate at which the transmitter and receiver operate. Bits B0 to B3 in the write-configuration register determine the baud-rate divisor (BRD), which divides down the X1 oscillator frequency. The baud clock is 16 times the data rate (baud rate). The transmitter section accepts SPI/Microwire data, formats it, and transmits it in asynchronous serial format from the TX output. Data is loaded into the transmitbuffer register from the SPI/Microwire interface. The MAX3100 adds start and stop bits to the data and clocks the data out at the selected baud rate (Table 7).
_______________________________________________________________________________________
5
SPI/Microwire-Compatible UART in QSOP-16 MAX3100
9 Pt TX-BUFFER REGISTER 9 Pt TX-SHIFT REGISTER D0t-D7t TX
SHDN DIN CS SCLK DOUT SPI INTERFACE B0 B1 B2 B3 X1 XTAL BAUD-RATE GENERATOR X2 FE START/STOPBIT DETECT RA ACTIVITY DETECT
Pr
RX-SHIFT REGISTER D0r-D7r
RX
9 (SOURCES) T R Pr RA/FE (MASKS) TRANSMIT-DONE (TM) IRQ INTERRUPT LOGIC DATA-RECEIVED (RM) PARITY (PM) FRAMING ERROR (RAM)/ RECEIVE ACTIVITY RTS 9 Pr Pr RX-BUFFER REGISTER RX-BUFFER REGISTER I/O
CTS
Figure 2. Functional Diagram
6
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SPI/Microwire-Compatible UART in QSOP-16 MAX3100
ONE BAUD PERIOD RX A
BAUD BLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MAJORITY CENTER SAMPLER
Figure 3. Start-Bit Timing
DATA UPDATED CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIN
1
1
FEN
SHDN
TM
RM
PM
RAM
IR
ST
PE
L
B3
B2
B1
B0
DOUT
R
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4. SPI Interface (Write Configuration)
The receiver section receives data in serial form. The MAX3100 detects a start bit on a high-to-low RX transition (Figure 3). An internal clock samples data at 16 times the data rate. The start bit can occur as much as one clock cycle before it is detected, as indicated by the shaded portion. The state of the start bit is defined as the majority of the 7th, 8th, and 9th sample of the internal 16x baud clock. Subsequent bits are also majority sampled. Receive data is stored in an 8-word FIFO. The FIFO is cleared if it overflows. The on-board oscillator can use a 1.8432MHz or 3.6864MHz crystal, or it can be driven at X1 with a 45% to 55% duty-cycle square wave.
SPI Interface
The bit streams for DIN and DOUT consist of 16 bits, with bits assigned as shown in the MAX3100 Operations section. DOUT transitions on SCLK's falling edge, and DIN is latched on SCLK's rising edge (Figure 4). Most operations, such as the clearing of internal registers, are executed only on CS's rising edge. The DIN stream is monitored for its first two bits to tell the UART the type of data transfer being executed (Write Config, Read Config, Write Data, Read Data). Only 16-bit words are expected. If CS goes high in the middle of a transmission (any time before the 16th bit), the sequence is aborted (i.e., data does not get written to individual registers). Every time CS goes low, a new 16-bit stream is expected. An example of a write configuration is shown in Figure 4.
7
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SPI/Microwire-Compatible UART in QSOP-16 MAX3100
MAX3100 Operations
Write Operations Table 1 shows write-configuration data. A 16-bit SPI/Microwire write configuration clears the receive FIFO and the R, T, RA/FE, D0r-D7r, D0t-D7t, Pr, and Pt registers. RTS and CTS remain unchanged. The new configuration is valid on CS's rising edge if the transmit buffer is empty (T = 1) and transmission is over. If the latest transmission has not been completed, the registers are updated when the transmission is over (T = 0). The write-configuration bits (FEN, SHDNi, IR, ST, PE, L, B3-B0) take effect after the current transmission is over. The mask bits (TM, RM, PM, RAM) take effect immediately after the 16th clock's rising edge at SCLK. Read Operations Table 2 shows read-configuration data. This register reads back the last configuration written to the
MAX3100. The device enters test mode if bit 0 = 1. In this mode, if CS = 0, the RTS pin acts as the 16x clock generator's output. This may be useful for direct baudrate generation (in this mode, TX and RX are in digital loopback). Normally, the write-data register loads the TX-buffer register. To change the RTS pin's state without writing data, set the TE bit. Setting the TE bit high inhibits the write command (Table 3). Reading data clears the R bit and interrupt IRQ (Table 4).
Register Functions
Table 5 shows read/write operation and power-on reset state (POR), and describes each bit used in programming the MAX3100. Figure 5 shows parity and wordlength control.
Table 1. Write Configuration (D15, D14 = 1, 1)
BIT DIN DOUT 15 1 R 14 1 T 13 FEN 0 12 SHDNi 0 11 TM 0 10 RM 0 9 PM 0 8 RAM 0 7 IR 0 6 ST 0 5 PE 0 4 L 0 3 B3 0 2 B2 0 1 B1 0 0 B0 0
Table 2. Read Configuration (D15, D14 = 0, 1)
BIT DIN DOUT 15 0 R 14 1 T 13 0 FEN 12 0 SHDNo 11 0 TM 10 0 RM 9 0 PM 8 0 RAM 7 0 IR 6 0 ST 5 0 PE 4 0 L 3 0 B3 2 0 B2 1 0 B1 0 TEST B0
Table 3. Write Data (D15, D14 = 1, 0)
BIT DIN DOUT 15 1 R 14 0 T 13 0 0 12 0 0 11 0 0 10 TE RA/FE 9 RTS CTS 8 Pt Pr 7 D7t D7r 6 D6t D6r 5 D5t D5r 4 D4t D4r 3 D3t D3r 2 D2t D2r 1 D1t D1r 0 D0t D0r
Table 4. Read Data (D15, D14 = 0, 0)
BIT DIN DOUT 15 0 R 14 0 T 13 0 0 12 0 0 11 0 0 10 0 RA/FE 9 0 CTS 8 0 Pr 7 0 D7r 6 0 D6r 5 0 D5r 4 0 D4r 3 0 D3r 2 0 D2r 1 0 D1r 0 0 D0r
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SPI/Microwire-Compatible UART in QSOP-16
Table 5. Bit Descriptions
BIT NAME B0-B3 B0-B3 CTS D0t-D7t D0r-D7r FEN FEN IR IR L L Pt READ/ WRITE w r r w r w r w r w r w POR STATE 0000 0000 No change X 00000000 0 0 0 0 0 0 X DESCRIPTION Baud-Rate Divisor Select Bits. Sets the baud clock's value (Table 6). Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers. Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = 0 implies CTS pin = logic high). Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored when L = 1. Eight data bits read from the receive FIFO or the receive register. These will be all 0s when the receive FIFO or the receive registers are empty. When L = 1, D7r is always 0. FIFO Enable. Enables the receive FIFO when FEN = 0. When FEN = 1, FIFO is disabled. FIFO-Enable Readback. FEN's state is read. Enables the IrDA timing mode when IR = 1. Reads the value of the IR bit. Bit for setting the word length of the transmitted or received data. L = 0 results in 8-bit words (9-bit words if PE = 1), see Figure 5. L = 1 results in 7-bit words (8-bit words if PE = 1). Reads the value of the L bit. Transmit-Parity Bit. This bit is treated as an extra bit that will be transmitted if PE = 1. To be useful in 9-bit networks, the MAX3100 does not calculate parity. If PE = 0, then this bit (Pt) is ignored in transmit mode (see the Nine-Bit Networks section). Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive data (see the Nine-Bit Networks section). Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt bit as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to be received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3100 does not calculate parity. Reads the value of the Parity-Enable bit. Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 6). Reads the value of the PM bit (Table 6). Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read from the receive register or FIFO. Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 6). Reads the value of the RM bit (Table 6). Mask for RA/FE bit. IRQ is asserted if RAM = 1 and RA/FE = 1 (Table 6). Reads the value of the RAM bit (Table 6). Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS bit = 0 sets the RTS pin = logic high).
MAX3100
Pr
r
X
PE
w
0
PE PM PM R RM RM RAM RAM RTS
r w r r w r w r w
0 0 0 0 0 0 0 0 0
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SPI/Microwire-Compatible UART in QSOP-16 MAX3100
Table 5. Bit Descriptions (continued)
BIT NAME READ/ WRITE POR STATE DESCRIPTION Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation, this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a framing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is expected. FE is set when a framing error occurs, and cleared upon receipt of the next properly framed character independent of the FIFO being enabled. When the device wakes up, it is likely that a framing error will occur. This error can be cleared with a write configuration. The FE bit is not cleared on a Read Data operation. When an FE is encountered, the UART resets itself to the state where it is looking for a start bit. Software-Shutdown Bit. Enter software shutdown with a write configuration where SHDNi = 1. Software shutdown takes effect after CS goes high, and causes the oscillator to stop as soon as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r-D7r, D0t-D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated while in shutdown. Exit software shutdown with a write configuration where SHDNi = 0. The oscillator restarts typically within 50ms of CS going high. RTS and CTS are unaffected. Refer to the Pin Description for hardware shutdown (SHDN input). Shutdown Read-Back Bit. The read-configuration register outputs SHDNo = 1 when the UART is in shutdown. Note that this bit is not sent until the current byte in the transmitter is sent (T = 1). This tells the processor when it may shut down the RS-232 driver. This bit is also set immediately when the device is shut down through the SHDN pin. Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmitted when ST = 1. The receiver only requires one stop bit. Reads the value of the ST bit. Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to accept another data word. Transmit-Enable Bit. If TE = 1, then only the RTS pin will be updated on CS's rising edge. The contents of RTS, Pt, and D0t-D7t transmit on CS's rising edge when TE = 0. Mask for T bit. IRQ is asserted if TM = 1 and T = 1 (Table 6). Reads the value of the TM bit (Table 6).
RA/FE
r
0
SHDNi
w
0
SHDNo
r
0
ST ST T TE TM TM
w r r w w r
0 0 1 0 0 0
PE = 0, L = 0 IDLE START D0 D1 D2 D3 D4 D5 D6 D7 STOP STOP IDLE
PE = 0, L = 1 IDLE START D0 D1 D2 D3 D4 D5 D6 STOP STOP IDLE
PE = 1, L = 0 IDLE START D0 D1 D2 D3 D4 D5 D6 D7 Pt STOP STOP IDLE
PE = 1, L = 1 IDLE TIME START D0 D1 D2 D3 D4 D5 D6 Pt STOP STOP IDLE
SECOND STOP BIT IS OMITTED IF ST = 0.
Figure 5. Parity and Word-Length Control
10 ______________________________________________________________________________________
SPI/Microwire-Compatible UART in QSOP-16 MAX3100
Interrupt Sources and Masks
A Read Data operation clears the interrupt IRQ. Table 6 gives the details for each interrupt source. Figure 6 shows the functional diagram for the interrupt sources and mask blocks.
Table 6. Interrupt Sources and Masks--Bit Descriptions
BIT NAME MASK BIT MEANING WHEN SET DESCRIPTION The Pr bit reflects the value in the word currently in the receive-buffer register (oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE = 0), or when parity is enabled and the received bit is 0. An interrupt is issued based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next value that will be read by a Read Data operation. The R bit is set when new data is available to be read from the receive register/ FIFO. FIFO is cleared when all data has been read. An interrupt is asserted as long as R = 1 and RM = 1. This is the RA (RX-transition) bit in shutdown, and the FE (framing-error) bit in operating mode. RA is set if there has been a transition on RX since entering shutdown. RA is cleared when the MAX3100 exits shutdown. IRQ is asserted when RA is set and RAM = 1. FE is determined solely by the currently received data, and is not stored in FIFO. The FE bit is set if a zero is received when the first stop bit is expected. FE is cleared upon receipt of the next properly framed character. IRQ is asserted when FE is set and RAM = 1. The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted low if TM = 1 and the transmit buffer becomes empty. This source is cleared on CS's rising edge during a Read Data operation. Although the interrupt is cleared, T may be polled to determine transmit-buffer status.
Pr
PM
Received parity bit = 1
R
RM
Data available
RA/FE
RAM
Transition on RX when in shutdown; framing error when not in shutdown
T
TM
Transmit buffer is empty
R
Q
S R
NEW DATA AVAILABLE DATA READ
T IRQ N Pr
RM MASK S TRANSMIT BUFFER EMPTY Q R DATA READ TM MASK Q S R PE = 1 AND RECEIVED PARITY BIT = 1 PE = 0 OR RECEIVED PARITY BIT = 0
PM MASK RA TRANSITION ON RX SHUTDOWN RAM MASK FRAMING ERROR SHUTDOWN RAM MASK
FE
Figure 6. Interrupt Sources and Masks Functional Diagram
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SPI/Microwire-Compatible UART in QSOP-16 MAX3100
Table 7. Baud-Rate Selection Table*
B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BAUD B2 B1 B0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0** 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DIVISION RATIO 1 2 4 8 16 32 64 128 3 6 12 24 48 96 192 384 BAUD RATE (fOSC = 1.8432MHz) 115.2k** 57.6k 28.8k 14.4k 7200 3600 1800 900 38.4k 19.2k 9600 4800 2400 1200 600 300 BAUD RATE (fOSC = 3.6864MHz) 230.4k** 115.2k 57.6k 28.8k 14.4k 7200 3600 1800 76.8k 38.4k 19.2k 9600 4800 2400 1200 600
Shutdown clears the receive FIFO, R, A, RA/FE, D0r-D7r, Pr, and Pt registers and sets the T bit high. Configuration bits (RM, TM, PM, RAM, IR, ST, PE, L, B0-3, and RTS) can be modified when SHDNo = 1 and CTS can also be read. Even though RA is reset upon entering shutdown, it will go high when any transitions are detected on the RX pin. This allows the UART to monitor activity on the receiver when in shutdown. The command to power up (SHDNi = 0) turns on the oscillator when CS goes high if SHDN pin = logic high, with a start-up time of about 25ms. This is done through a write configuration, which clears all registers but RTS and CTS. Since the crystal oscillator typically requires 25ms to start, the first received characters will be garbled, and a framing error may occur.
__________Applications Information
Driving Opto-Couplers
Figure 7 shows the MAX3100 in an isolated serial interface. The MAX3100 Schmitt-trigger inputs are driven directly by opto-coupler outputs. Isolated power is provided by the MAX845 transformer driver and linear regulator shown. A significant feature of this application is that the opto-coupler's skew does not affect the asynchronous serial output's timing. Only the set-up and hold times of the SPI interface need to be met. Figure 8 shows a bidirectional opto-isolated interface using only two opto-isolators. Over 81% power savings is realized using IrDA mode due to its 3/16-wide baud periods.
*Standard baud rates shown in bold **Default baud rate
Clock-Oscillator Baud Rates
Bits B0-B3 of the write-configuration register determine the baud rate. Table 7 shows baud-rate divisors for given input codes, as well as the given baud rate for 1.8432MHz and 3.6864MHz crystals. Note that the baud rate = crystal frequency / 16x division ratio.
Crystal-Oscillator Operation-- X1, X2 Connection
The MAX3100 includes a crystal oscillator for baud-rate generation. For standard baud rates, use a 1.8432MHz or 3.6864MHz crystal. The 1.8432MHz crystal results in lower operating current; however, the 3.6864MHz crystal may be more readily available in surface mount. Ceramic resonators are low-cost alternatives to crystals and operate similarly, though the "Q" and accuracy are lower. Some ceramic resonators are available with integral load capacitors, which can further reduce cost. The tradeoff between crystals and ceramic resonators is in initial frequency accuracy and temperature drift. The total error in the baud-rate generator should be kept below 1% for reliable operation with other systems. This is accomplished easily with a crystal, and in most cases can be achieved with ceramic resonators. Table 8 lists the different types of crystals and resonators and their suppliers.
Shutdown Mode
In shutdown, the oscillator turns off to reduce power dissipation (I CC < 10A). The MAX3100 enters shutdown in one of two ways: by a software command (SHDNi bit = 1) or by a hardware command (SHDN = logic low). The hardware shutdown is effective immediately and will immediately terminate any transmission in progress. The software shutdown, requested by setting SHDNi bit = 1, is entered upon completing the transmission of the data in both the transmit register and the transmit-buffer register. The SHDNo bit is set when the MAX3100 enters shutdown (either hardware or software). The microcontroller (C) can monitor the SHDNo bit to determine when all data has been transmitted, and shut down any external circuitry (such as RS-232 transceivers) at that time.
12
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SPI/Microwire-Compatible UART in QSOP-16 MAX3100
ISO +5V
2k VCC 6N136 DIN
470 DOUT
MAX3100
ISO +5V
2k VCC
MAX3222
6N136 SCLK TX RX
470 SCLK VCC RTS 2k 470 DIN 6N136 CTS
DOUT
2k VCC 6N136 CS
470 CS +5V MBR0520
MAX667 LINEAR REGULATOR
ISO 5V
MAX253
TRANSFORMER DRIVER HALO TGM-010P3
Figure 7. Driving Optocouplers
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13
SPI/Microwire-Compatible UART in QSOP-16 MAX3100
+5V ISO +5V
VCC TX CS SCLK DIN DOUT 470
2k RX
VCC
CS SCLK
MAX3100
+5V
MAX3100
DIN DOUT
2k RX GND 470 TX GND
Figure 8. Bidirectional Opto-Isolated Interface
Table 8. Component and Supplier List
DESCRIPTION Through-Hole Crystal (HC-49/U) Through-Hole Resonator Through-Hole Crystal (HC-49/US) SMT Crystal SMT Resonator FREQUENCY (MHz) 1.8432 1.8432 3.6864 3.6864 3.6864 TYPICAL C1, C2 (pF) 25 47 33 39 None (integral) SUPPLIER ECS International, Inc. Murata North America ECS International, Inc. ECS International, Inc. AVX/Kyocera PART NUMBER ECS-18-13-1 CSA1.84MG ECS-36-18-4 ECS-36-20-5P PBRC-3.68B PHONE NUMBER (913) 782-7787 (800) 831-9172 (913) 782-7787 (913) 782-7787 (803) 448-9411
This oscillator supports parallel-resonant mode crystals and ceramic resonators, or can be driven from an external clock source. Internally, the oscillator consists of an inverting amplifier with its input, X1, tied to its output, X2, by a bias network that self-biases the inverter at approximately VCC / 2. The external feedback circuit, usually a crystal, from X2 to X1 provides 180 of phase shift, causing the circuit to oscillate. As shown in the standard application circuit, the crystal or resonator is connected between X1 and X2, with the load capacitance for the crystal being the series combination of C1 and C2. For example, a 1.8432MHz crystal with a spec14
ified load capacitance of 11pF would use capacitors of 22pF on either side of the crystal to ground. Series-resonant mode crystals have a slight frequency error, typically oscillating 0.03% higher than specified seriesresonant frequency, when operated in parallel mode. It is very important to keep crystal, resonator, and load-capacitor leads and traces as short and direct as possible. The X1 and X2 trace lengths and ground tracks should be tight, with no other intervening traces. This helps minimize parasitic capacitance and noise pickup in the oscillator, and reduces EMI. Minimize capacitive loading on X2 to minimize supply current.
______________________________________________________________________________________
SPI/Microwire-Compatible UART in QSOP-16
The MAX3100 X1 input can be driven directly by an external CMOS clock source. The trip level is approximately equal to V CC / 2. No connection should be made to X2 in this mode. If a TTL or non-CMOS clock source is used, AC couple with a 10nF capacitor to X1. The peak-to-peak swing on the input should be at least 2V for reliable operation. The parity/9th-bit interrupt is controlled only by the data in the receive register, and is not affected by data in the FIFO, so the most effective use of the parity/9th-bit interrupt is with FIFO disabled. With the FIFO disabled, received nonaddress words can be ignored and not even read from the UART.
MAX3100
SIR IrDA Mode
The MAX3100's IrDA mode can be used to communicate with other IrDA SIR-compatible devices, or to reduce power consumption in opto-isolated applications. In IrDA mode, a bit period is shortened to 3/16 of a baud period (1.6s at 115,200 baud) (Figure 9). A data zero is transmitted as a pulse of light (TX pin = logic low, RX pin = logic high). In receive mode, the RX signal's sampling is done halfway into the transmission of a high level. The sampling is done once, instead of three times, as in normal mode. The MAX3100 ignores pulses shorter than approximately 1/16 of the baud period. The IrDA device that is communicating with the MAX3100 must be set to transmit pulses at 3/16 of the baud period. For compatibility with other IrDA devices, set the format to 8-bit data, one stop, no parity.
9-Bit Networks
The MAX3100 supports a common multidrop communication technique referred to as 9-bit mode. In this mode, the parity bit is set to indicate a message that contains a header with a destination address. The MAX3100 parity mask can be set to generate interrupts for this condition. Operating a network in this mode reduces the processing overhead of all nodes by enabling the slave controllers to ignore most message traffic. This can relieve the remote processor to handle more useful tasks. In 9-bit mode, the MAX3100 is set up with 8 bits plus parity. The parity bit in all normal messages is clear, but is set in an address-type message. The MAX3100 parity-interrupt mask is enabled to generate an interrupt on high parity. When the master sends an address message with the parity bit set, all MAX3100 nodes issue an interrupt. All nodes then retrieve the received byte to compare to their assigned address. Once addressed, the node continues to process each received byte. If the node was not addressed, it ignores all message traffic until a new address is sent out by the master.
IrDA Module The MAX3100 was optimized for direct optocoupler drive, whereas IrDA modules contain inverting buffers. Invert the RX and TX outputs as shown in Figure 10. 8051 Example: IrDA to RS-232 Converter Figure 10 shows the MAX3100 with an 8051 C. This circuit receives IrDA data and outputs standard RS-232 data. Although the 8051 contains an internal UART, it does not support IrDA or high-speed communications. The MAX3100 can easily interface to the 8051 to support these high-performance communications modes. The 8051 does not have an SPI interface, so communication with the MAX3100 is accomplished with port pins and a short software routine (Figure 12a). The software routine polls the IRQ output to see if data is available from the MAX3100 UART. It then shifts the data out, using the 8051 port pins, and transmits it out the RS-232 side through the MAX3221 driver. The 8051 simultaneously monitors its internal UART for incoming communications from the RS-232 side, and transmits this data out the IrDA side through the MAX3100. The low-level routine (UTLK) is the core routine that sends and receives data over the port pins to simulate an SPI port on the 8051. This technique is useful for any 8051based MAX3100 port-pin-interfaced application.
NORMAL UART TX IrDA TX IrDA RX NORMAL RX
START
1
0
1
0
0
1
1
0
0 START
1
0
1
0
0
1
1
0
DATA BITS UART FRAME
Figure 9. IrDA Timing
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STOP
STOP 1 1
15
SPI/Microwire-Compatible UART in QSOP-16 MAX3100
DIRECT OPTO-COUPLER DRIVE +5V 330 IR MODULE DRIVE
OR
MAX3221
TX +5V 8051
IR LED TX 1/6 HC00 TXD IR MODULE
MAX3100
0.1F IRQ 1.8432MHz RX
100
3100
RX 10k 1/6 HC00
RXD
22pF
22pF
Figure 10. Bidirectional RS-232 IrDA Using an 8051
Interface to PIC Processor ("Quick Brown Fox" Generator)
Figure 11 illustrates the use of the MAX3100 with the PIC(R). This circuit is a "Quick Brown Fox" generator that repeatedly transmits "THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG" (covering the entire alphabet) over an RS-232 link with adjustable baud rate, word length, and delay. Although a software-based UART could be implemented on the PIC, features like accurate variable baud rates, high baud rates, and simple protocol selection would be difficult to implement reliably. The 16C54 in the example is the most basic of the PICs. Thus, it is possible to implement the example on any member of the PIC family.
The software routine (Figure 12) begins by reading the DIP switch on port RB. The switch data includes 4 bits for the baud rate, 1 bit for number of stop bits, 1 bit for a word length of 7 or 8 bits, and 1 bit for delay between messages. The PIC reads the switch only at initialization (reset), and programs the parameters into the MAX3100. It then begins sending the message repeatedly. If the delay bit is set, it inserts a 1sec delay between transmissions. As in the 8051 example, the main routine is called UTLK, and can be used in any PIC-based, port-pin-interfaced application.
PIC is a registered trademark of Microchip Corporation.
16
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SPI/Microwire-Compatible UART in QSOP-16 MAX3100
VCC
GO 100k Y/N 1s Delay 100k
RB7
PIC16C54 RB6 RA0 DOUT
MAX3221 MAX3100
1/2 STOP BITS 100k 7/8 BITS 100k RB4 RA2 SCLK RB5 RA1 DIN TX TX
B3 100k
RB3
RA3
CS X1 X2
B2 100k
RB2
1. 8432MHz 22pF 22pF
B1 100k
RB1
B0
RB0
100k
Figure 11. Quick Brown Fox Generator
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17
SPI/Microwire-Compatible UART in QSOP-16 MAX3100
__________MAX3100 Synchronous-to-Asynchronous SPI UART at a Glance
Table 9. Synchronous Data Input Format (DIN pin from microprocessor, SPI MOSI)
Bit Number Operation Write Config Read Config Write Data Read Data 15 1 0 1 0 14 1 1 0 0 13 FEN 0 0 0 12 SHDNi 0 0 0 11 TM 0 0 0 10 RM 0 TE 0 9 PM 0 RTS 0 8 RAM 0 Pt 0 7 IR (IrDA) 0 D7t 0 6 ST 0 D6t 0 5 PE 0 D5t 0 4 L 0 D4t 0 3 B3 0 D3t 0 2 B2 0 D2t 0 1 B1 0 D1t 0 0 B0 TEST D0t 0
Table 10. Synchronous Data Output Format (DOUT pin to microprocessor, SPI MISO)
Bit Number Operation Write Config Read Config Write Data Read Data 15 R R R R 14 T T T T 13 0 FEN 0 0 12 0 SHDNo 0 0 11 0 TM 0 0 10 0 RM RA/ FE RA/ FE 9 0 PM CTS CTS 8 0 RAM Pr Pr 7 0 IR (IrDA) D7r D7r 6 0 ST D6r D6r 5 0 PE D5r D5r 4 0 L D4r D4r 3 0 B3 D3r D3r 2 0 B2 D2r D2r 1 0 B1 D1r D1r 0 0 B0 D0r D0r
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SPI/Microwire-Compatible UART in QSOP-16 MAX3100
Table 11. Bit Definitions*
Register Config Config Config Bit Name FEN SHDNi TM Bit Set (1) Disable FIFO buffer Shutdown Enable transmitdone interrupt Enable datareceived interrupt Enable parity interrupt Enable framingerror interrupt Enable IrDA timing mode Two stop bits Parity enabled Bit Clear (0) Enable FIFO buffer Operate Disable transmitdone interrupt Disable datareceived interrupt Disable parity interrupt Disable framingerror interrupt Standard timing One stop bit Parity disabled Register Config Write Data Write Data Write Data Read Data Read Data All All Bit Name L TE RTS Pt RA/FE CTS R T Bit Set (1) Word length = 7 bits Inhibit TX output Drive RTS output pin low Transmit parity = 1 Data overrun or framing error CTS input pin is low Data has been received Transmit buffer is empty Bit Clear (0) Word length = 8 bits Enable normal operation Drive RTS output pin high Transmit parity = 0 Normal CTS input pin is high Data buffer is empty UART is busy transmitting
Config
RM
Config Config Config Config Config
PM RAM IR ST PE
*Default setting is clear
Table 12. Field Definitions
Register Config Write Data Read Data Read Data Field Name B3-B0 D7t-D0t Pr D7r-D0r Meaning Baud-rate divisor Transmit data Received parity bit Received data
Table 13. 1.8432MHz Baud Rates
B3...B0 0 000 0 001 0 010 0 011 0 100 0 101 0 110 0 111 BRD 1 2 4 8 16 32 64 128 Baud 115.2k 56k 28k 14k 7200 3600 1800 900 B3...B0 1 000 1 001 1 010 1 011 1 100 1 101 1 110 1 111 BRD 3 6 12 24 48 96 192 384 Baud 38.4k 19.2k 9600 4800 2400 1200 600 300
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19
SPI/Microwire-Compatible UART in QSOP-16 MAX3100
Figure 12a. 8051 IrDA/RS-232 Code
20 ______________________________________________________________________________________
SPI/Microwire-Compatible UART in QSOP-16 MAX3100
Figure 12b. MAX3100 Using PIC C
______________________________________________________________________________________ 21
SPI/Microwire-Compatible UART in QSOP-16 MAX3100
Figure 12b. MAX3100 Using PIC C (continued)
22 ______________________________________________________________________________________
SPI/Microwire-Compatible UART in QSOP-16
___________________________________________________Typical Operating Circuit
MAX3100
SPI/MICROWIRE DIN
MAX3100
TX
MAX3223
RS-232 I/O
C
DOUT
RX
SCLK
CTS
CS
RTS
IRQ
C1
C2
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23
SPI/Microwire-Compatible UART in QSOP-16 MAX3100
___________________Chip Information
TRANSISTOR COUNT: 6848 SUBSTRATE CONNECTED TO GND
________________________________________________________Package Information
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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